8P79818NLGI8

8P79818NLGI8 is a programmable low additive jitter 2:8 buffer with dividers and universal outputs. The device is intended to take 1 or 2 reference clocks, select between them, using a pin or register selection and generate up to 8 outputs that may be the same as the reference frequency or integer-divider versions of it. This supports two output banks, each with its own divider and power supply. All outputs in one bank would generate the same output frequency, but each output can be individually controlled for output type, output enable or even powered-off. The device supports a serial port for configuration of the parameters while in operation. The serial port can be selected to use the I²C or SPI protocol. After power-up, all outputs will come up in LVDS mode and may be programmed to other configurations over the serial port. Outputs may be enabled or disabled under control of the OE input pin.

• Two differential inputs support LVPECL, LVDS, HCSL or LVCMOS reference clocks
• Accepts input frequencies ranging from 1PPS (1Hz) to 700MHz
• Switchover will not generate any runt clock pulses on the output
• Differential outputs selectable as LVPECL, LVDS, CML or HCSL
• Differential outputs support frequencies from 1PPS to 700MHz
• LVCMOS outputs support frequencies from 1PPS to 200MHz
• LVCMOS outputs in the same pair may be inverted or in-phase relative to one another
• Outputs arranged in 2 banks of 4 outputs each
• Output enable control pin, register programmable via I2C / SPI serial port
• 32 lead VFQFN package, ambient operating temperature range from -40°C to +85°C