HEF4040BP

The HEF4040BP is a 12-stage binary Ripple Counter with a clock input (CP), an overriding asynchronous master reset input (MR) and twelve fully buffered outputs (Q0 to Q11). The counter advances on the high-to-low transition of CP. A high on MR clears all counter stages and forces all outputs low, independent of CP. Each counter stage is a static toggle flip-flop. The clock input is highly tolerant of slow rise and fall times due to its Schmitt trigger action.

• Tolerant of slow clock rise and fall time
• Fully static operation
• Standardized symmetrical output characteristics
• Complies with JEDEC standard JESD 13-B

Applikationer

Industrial, Clock & Timing