74LVC2G125DC,125

74LVC2G125DC,125 is a dual bus buffer/line driver with 3-state outputs controlled by the output enable inputs (n active-low OE). Inputs can be driven from either 3.3V or 5V devices. This feature allows the use of this device as a translator in mixed 3.3V and 5V environments. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. This device is fully specified for partial-power-down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down. It complies with JEDEC standard (JESD8-7 (1.65V to 1.95V), JESD8-5 (2.3V to 2.7V), JESD8C (2.7V to 3.6V), JESD36 (4.5V to 5.5V). It features ESD protection (HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000V, CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000V).

• Wide supply voltage range from 1.65V to 5.5V
• High noise immunity, IOFF circuitry provides partial power-down mode operation
• CMOS low-power consumption, latch-up performance exceeds 250mA
• Direct interface with TTL levels, overvoltage tolerant inputs to 5.5V
• Input leakage current is ±0.1μA typ at (VI=5.5V or GND;VCC = 0V to 5.5V, -40°C to +85°C)
• Supply current is 0.1μA typ at (VI=5.5V or GND;VCC = 1.65V to 5.5V;IO = 0A, -40°C to +85°C)
• Propagation delay is 3.7ns typical at (VCC = 1.65V to 1.95V, -40°C to +85°C)
• Operating temperature range from -40°C to +125°C
• VSSOP8 package

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