IS42S16800F-7BLI

IS42S16800F-7BLI is a 128Mb synchronous DRAM that achieves high-speed data transfer using pipeline architecture. All inputs and outputs signals refer to the rising edge of the clock input. It is a high speed CMOS, dynamic random-access memory designed to operate in 3.3V Vdd and 3.3V Vddq memory systems containing 134,217,728 bits. Internally configured as a quad-bank DRAM with a synchronous interface. Each 33,554,432bit bank is organized as 4,096 rows by 512 columns by 16 bits or 4,096 rows by 1,024 columns by 8 bits. The 128Mb SDRAM includes an AUTO REFRESH MODE, and a power-saving, power-down mode. All signals are registered on the positive edge of the clock signal, CLK. All inputs and outputs are LVTTL compatible.

• Fully synchronous; all signals referenced to a positive clock edge
• Internal bank for hiding row access/precharge, LVTTL interface, self refresh
• Programmable burst sequence: sequential/interleave, auto refresh (CBR)
• Random column address every clock cycle, programmable active-low CAS latency (2, 3 clocks)
• Burst read/write and burst read/single write operations capability
• Burst termination by burst stop and precharge command
• 143MHz frequency, 7ns speed
• 54-ball BGA package
• Industrial temperature rating range from -40°C to +85°C