S25FL128SAGMFV003

S25FL128SAGMFV003 is a S25FL128S FL-S flash memory. This family of devices connect to a host system via a SPI. Traditional SPI single bit serial input and output (single I/O or SIO) is supported as well as optional two bit (dual I/O or DIO) and four bit (Quad I/O or QIO) serial commands. This multiple width interface is called SPI Multi-I/O or MIO. In addition, the FL-S family adds support for DDR read commands for SIO, DIO, and QIO that transfer address and read data on both edges of the clock. The Eclipse architecture features a page programming buffer that allows up to 128 words (256 bytes) or 256 words (512 bytes) to be programmed in one operation, resulting in faster effective programming and erase than prior generation SPI program or erase algorithms.

• 128MB density, 133MHz speed, 65-nm MIRRORBIT™ process technology
• Uniform 64KB sectors with Hybrid 4KB sectors
• Normal, fast, dual, quad, fast DDR, dual DDR, quad DDR read commands
• Common flash interface (CFI) data for configuration information
• Quad-input page programming (QPP) for slow clock systems
• 100,000 minimum program-erase cycles, 20 year minimum data retention cycling endurance
• Individual sector protection controlled by boot code or password
• Core supply voltage range from 2.7V to 3.6V
• 16-pin SO package, industrial plus temperature range from -40°C to + 105°C

Advarsler

Market demand for this product has caused an extension in leadtimes. Delivery dates may fluctuate. Product exempt from discounts.