S80KS2564GACHV040

S80KS2564GACHV040 is a 256Mb HYPERRAM™ self-refresh DRAM (PSRAM). The DRAM array uses dynamic cells that require periodic refresh. Refresh control logic within the device manages the refresh operations on the DRAM array when the memory is not being actively read or written by the HYPERBUS™ extended-IO host. Since the host is not required to manage any refresh operations, the DRAM array appears to the host as though the memory uses static cells that retain data without refresh. Hence, the memory is more accurately described as pseudo static RAM (PSRAM). Since the DRAM cells cannot be refreshed during a read or write transaction, there is a requirement that the host limit read or write burst transfers lengths to allow internal logic refresh operations when they are needed.

• HYPERBUS™ extended-IO, 1.7 to 2V (1.8 typical) interface support
• Single-ended clock (CK) - 20 bus signals, chip select (CS#), hardware reset (RESET#)
• Bidirectional read-write data strobe (RWDS 1:0), input during write transactions as write data mask
• Output at the start of all transactions to indicate refresh latency
• 200MHz maximum clock rate, DDR - transfers data on both edges of the clock
• Configurable output drive strength, hybrid sleep mode, deep power down
• Industrial operating temperature range from –40°C to +105°C
• 49-ball FBGA package
• 25nm DRAM technology
• Output during read transactions as read data strobe