SN74LVC1G125DRLR

The SN74LVC1G125DRLR is a single Bus Buffer Gate with 3-state outputs. The output is disabled when the output-enable (OE) input is high. The CMOS device has high output drive while maintaining low static power dissipation over a broad VCC operating range. The device contains one buffer gate device with output enable control and performs the Boolean function Y = A. This device is fully specified for partial-power-down applications using IOFF. The IOFF circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pull-up resistor and the minimum value of the resistor is determined by the current-sinking capability of the driver.

• Provides down translation to VCC
• IOFF Supports live insertion, partial-power-down mode and back-drive protection
• Latch-up performance exceeds 100mA per JESD 78, class II
• Inputs accept voltages to 5.5V
• 3.7ns at 3.3V Propagation delay (tpd)
• 10µA ICC Low power consumption
• ±24mA Output drive at 3.3V
• Green product and no Sb/Br

Applikationer

Communications & Networking, Automation & Process Control, Aerospace, Defence, Military, Motor Drive & Control, Signal Processing, Imaging, Video & Vision, Computers & Computer Peripherals, RF Communications, Multimedia