CD74HC165E

The CD74HC165E is a 8-bit CMOS parallel-in/serial-out Shift Register with the complementary serial outputs (Q7 and Q7\) available from the last stage. When the parallel load (PL\) input is low, parallel data from the D0 to D7 inputs are loaded into the register asynchronously. When the PL\ is high, data enters the register serially at the DS input and shifts one place to the right (Q0 → Q1 → Q2, etc.) with each positive-going clock transition. This feature allows parallel-to-serial converter expansion by typing the Q7 output to the DS input of the succeeding device. For predictable operation the low-to-high transition of CE\ should only take place while CP is high. Also, CP and CE\ should be low before the low-to-high transition of PL to prevent shifting the data when PL\ goes high.

• Buffered inputs
• Asynchronous parallel load
• Complementary outputs
• Balanced propagation delay and transition times
• Significant power reduction compared to LSTTL logic ICs
• High noise immunity
• Direct LSTTL input logic compatibility
• CMOS Input compatibility
• 10 LSTTL Loads standard outputs
• 15 LSTTL Loads bus driver outputs

Applikationer

Communications & Networking